Instantiation

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Instantiation is one of the interactive graphs Understand can draw of your code — call trees, dependencies, control flow, and more.

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Instantiation

Languages: VHDL
Targets: Entity Units
Variants: Custom

Show the instantiation hierarchy of a selected VHDL entity or architecture: which entities it instantiates, and which architectures implement each of those, recursively.

Each box is a specific entity/architecture pair, split into two fields — the entity's name on top, and the implementing architecture's name below. An edge leads from an architecture to each entity it instantiates, including ones instantiated inside a nested block or generate statement; enabling Show Count labels each edge with how many times that entity is instantiated. A component instantiation is resolved to whatever entity it's bound to; an entity that can't be resolved, or one that's still just an unbound component, is drawn as a gray octagon instead.

Rooted at the structural architecture of system below, the graph shows it instantiating cpu (using its structural architecture), memory, and bus_ctrl (each using their behavioral architecture). cpu's own structural architecture in turn instantiates alu and registers, both using their behavioral architecture; neither instantiates anything further, so the tree ends there.

See the following code and corresponding graph

entity system is
  port (
    clk : in std_logic;
    req : in std_logic
  );
end entity system;

architecture structural of system is
  signal we      : std_logic := '0';
  signal grant   : std_logic;
  signal cpu_out : std_logic_vector(7 downto 0);
  signal mem_out : std_logic_vector(7 downto 0);
begin
  u_cpu : entity work.cpu(structural)
    port map (clk => clk, we => we, din => mem_out, dout => cpu_out);

  u_mem : entity work.memory(behavioral)
    port map (clk => clk, we => we, din => cpu_out, dout => mem_out);

  u_bus : entity work.bus_ctrl(behavioral)
    port map (clk => clk, req => req, grant => grant);
end architecture structural;

entity cpu is
  port (
    clk  : in  std_logic;
    we   : in  std_logic;
    din  : in  std_logic_vector(7 downto 0);
    dout : out std_logic_vector(7 downto 0)
  );
end entity cpu;

architecture structural of cpu is
  signal alu_out : std_logic_vector(7 downto 0);
  signal reg_out : std_logic_vector(7 downto 0);
begin
  u_alu : entity work.alu(behavioral)
    port map (clk => clk, a => din, b => reg_out, result => alu_out);

  u_regs : entity work.registers(behavioral)
    port map (clk => clk, we => we, din => alu_out, dout => reg_out);

  dout <= reg_out;
end architecture structural;

entity alu is
  port (
    clk    : in  std_logic;
    a, b   : in  std_logic_vector(7 downto 0);
    result : out std_logic_vector(7 downto 0)
  );
end entity alu;

architecture behavioral of alu is
begin
  -- ...
end architecture behavioral;

entity registers is
  port (
    clk  : in  std_logic;
    we   : in  std_logic;
    din  : in  std_logic_vector(7 downto 0);
    dout : out std_logic_vector(7 downto 0)
  );
end entity registers;

architecture behavioral of registers is
begin
  -- ...
end architecture behavioral;

entity memory is
  port (
    clk  : in  std_logic;
    we   : in  std_logic;
    din  : in  std_logic_vector(7 downto 0);
    dout : out std_logic_vector(7 downto 0)
  );
end entity memory;

architecture behavioral of memory is
begin
  -- ...
end architecture behavioral;

entity bus_ctrl is
  port (
    clk   : in  std_logic;
    req   : in  std_logic;
    grant : out std_logic
  );
end entity bus_ctrl;

architecture behavioral of bus_ctrl is
begin
  -- ...
end architecture behavioral;

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